TEXAS INSTRUMENTS
CAMPUS INTERVIEW – July 28th 2001
2 Tests : Technical + Aptitude
Both the tests are of objective type.
About Technical Test:
Technical:4 Sections 1) PDS 2) Computer Architecture 3) Digital 4) Analog .
Technical :Time :60 minutes
Questions: 10 questions in each section.
You have to write any two out of the four sections.
Each right answer gets you 1 mark.For a wrong
Answer 0.5 is deducted.
There are two broad divisions in Texas into which the
students get placed. One is the software section and the other is the hardware section.
To get into Hardware section, you should choose Analog as one of your sections in the technical test.
About Aptitude Test:
Aptitude: Time 60 minutes
Questions: 75 questions.
Same negative marking applies here too!
Correct 1 mark
Wrong -0.5 mark
The questions are similar to CAT exam. There are no
Verbal questions.
The following are the questions that are asked in the
Digital and analog Section:
DIGITAL:
1) For the output y= ab+a’c+bc where a,b and c are input boolean variables
a) the output glitches and the output can be reduced
b) the output will not glitch and the output can be
reduced
c) the output glitches and the output cannot be
reduced
d) the output will not glitch and the output cannot be
reduced.
2) A function is given . The given function is identical
to
choices: 4 different representations of the given fn.
To answer this question we should use K-map and
reduce the given fn. Then reduce each of the fns in
the choices and see if they are equal. Simple but
time consuming. 
Note: My diagram is not exact.I hope you know the correct diagram of CMOS NAND gate. Take care !
Now an input sequence is given . AB=01->11->10->00
The output logic level at point X is asked. Choices are
given like a) 5v->4v->0v->0v, b)0v->0v->4v->unknown
c) 5v->5v->0v->4v etc.
I am not sure about any of the sequences given above.
but the question here is to test whether we can find
when a MOSFET is open and when it is closed.
when both the lower MOSFETs are open the output
X is free floating.So its voltage is unknown. The
choice answer is b) but this may not be the answer for
the input sequence given above simply because I
don’t remember the exact sequence given in the Q-paper.
The given state diagram corresponds to
a) an n-bit binary counter
b) an n-bit gray counter
c) a 2 bit binary to gray code converter
d) a 2 bit gray code to binary converter
5) Two D-flip flops connected as Shift registers. But in the
connection between Qa and Db two not gates in series are
introduced. Then there is a feedback from output of the
second flipflop to the first one through a line containing
delays using even no of not gates.
Don’t try to draw a circuit based on these information.
I don’t remember the circuit. I am just telling this to help
you learn the concept related to this.
The D-flipflops are clocked using a single clock source.
It was asked that for proper working what is the relation
between the minimum clk period and the propagation
delay of the D-flip flop.
I know this question is incomplete and you have lot of
doubts. But this question should atleast tell you to
learn the timing diagrams and relation between clk
period and propagation delay of flipflops.
Two Tri-state buffers are shown above. A 4 bit counter (natural count) output is connected to the 4 inputs A,B,C
And D such that the MSB is connected to D and LSB to
A. For how many counter states the circuit is sure to
produce proper output ?
Choices are given.
Answer: Whenever the LSB and second MSB are complement to each other the circuit is sure to give
proper output(either B or D). For all other inputs
the output is either floating or allows both B and
D to the o/p simultaneously.
So write the counter o/p and count the no of o/ps
for which A and C are complement to each other.
That’s the answer. Am I right ?.
For this circuit the relation between input clk and the output B is asked.
If you work it out you will find that the output B has
¼ th the clk frequency and its duty cycle is 50 %.
The choices given are
a) ½ the clk frequency and 25 %duty cycle.
b) 1/3 rd the clk frequency and 50% duty cycle.
c) 1/4th the clk frequency and 50 % duty cycle.
d) ½ the clk frequency and 50 % duty cycle.
The system is initially in state Sa. If * represents zero or
more occurrence of a logic level and + represents one or
more occurrence of a logic level which of the following
best describes the sequence of states the system could
have gone through if it is finally in state Sc.
a) 0*-> 1+ ->0 +
b) 0*->1*->1*
c) 0*->0*->1
d) 0+->1+-> 0*
Note:The answer choices are only a wild guess. The
answer is a). This is just like an aptitude test question.
There are 2 more questions in this section. I don’t remember them.Sorry!
For this circuit the time constant is
a) RC
b) RC
c) 0
d) RC/2
d) All Pass filter
2)
All diode drops are 0.7 V .The Vbe voltage is 0.7V if forward biased. What is the voltage Vo
a)1.4 V
b) 2V
c)0V
d)2.3 V
There are 3 more questions.Again I am sorry .I don’t remember them.
Questions I was asked in the Interview:
1) definition of setup time and hold time
2) internal diagram of NAND gate(either TTL or CMOS)
3) R-S flip flop diagram using NAND gates
4) Race condition in R-S F/F. Both R and S are given
Logic 0.The o/p is 11. Then both inputs switched to
Logic 0 simultaneously.What is the o/p ?. Answer
:Not predictable.Depends on prop delay.
5) Diagram of CE Amplifier and Calculation of
Amplifier gain.
6) Op-amp : +ve pin to ground. Input through a resistor
And capacitor in series to the –ve input. Feedback:
R and C in parallel.
Asked to find the transfer function,plot the Bode plot,
and the Pole-Zero plot.
7) Passive integrator and differentiator circuit. Asked to
Write eqns for charging and discharging .
8) Given a circuit with 2 opamps . The circuit was like
The instrumentation amplifier.If you know to analyse
The instrumentation amplifier this circuit is pretty easy.
9) Current mirror. How it acts as a current source?.
10) Voltage follower using op-amp. Asked to draw the
frequency response of voltage follower and compare it
with that of open-loop response.Asked to derive the relation between open-loop cut-off frequency and closed-loop cut-off frequency.
10) Asked to implement NOT gate using 2 to 1 MUX.
11) Asked why we write 00 01 11 10 in that order while
Drawing K-maps.
